Advanced Analog Front-End Design

Our highly-differentiated Analog Front-End (AFE) is composed of best-in-class high-speed and high-resolution analog-to-digital and digital-to-analog converters (ADCs and DACs) which provide the interface between the real-world signal coming from the cables and the digital processing engine.

Mixed-Mode Signal Processing Architecture (MMSP)

We have designed a novel analog architecture that we call MMSP, which provides a different partitioning of signal processing between the analog and digital domains, leading to optimized power and die size.

Multi-Core Signal Processor Architecture (MCSP)

We use our proprietary transistor-level implementation and mapping techniques to create highly efficient multi-core processing engines, which we call MCSPs.

Advanced power management techniques

By combining innovative techniques based on back biasing and voltage scaling, our engineers were able to significantly reduce the impact of static and dynamic leakage power.

THE IEEE® 802.3bzTM STANDARD

Together with Cisco, Freescale and Xilinx, we formed the NBASE-T Alliance, a not-for-profit organization dedicated to the development and promotion of the 5G/2.5G technology. Aquantia is the first company in over 40 years of Ethernet existence to have a standard created purely from its own technology. We are the sole inventor of AQrate technology and the only supplier of multigigabit ICs in production today. Aquantia played a key role is pushing the Multi-Gigabit technology through the standardization process within IEEE. In September 2016, IEEE officially approved IEEE® 802.3bzTM as a standard, a record timeframe of less than 2 years from proposal to approval.

hotchips

FIVE-SPEED PHY ENABLES 5Gbps & 2.5Gbps ETHERNET RATES
OVER LEGACY COPPER CABLES

technology_ramin_fRAMIN FARJADRAD, PhD
VP Technology Development @ CEO Office

Ramin Farjadrad received his B.Sc. from Sharif Univ. and M.Sc. & Ph.D. from Stanford Univ. in EECS. Ramin has established himself as a leading architect of high performance communications chips with wide range of expertise in mixed-signal ICs, signal processing and coding.+BioLess –

Ramin started his career at SUN Micro in 1995 and was later at LSI Logic in 1996, where he developed various multi-Gbps SerDes architectures. His PhD project at Stanford led to the first 10Gbps PAM4 CMOS SerDes in 1999. Ramin also co-founded Velio Communications in 1999, where he focused on the development of CMOS Terabit switch chips as company chief engineer. He then served as Sr. principal architect following Velio acquisition by Rambus in 2003. Ramin joined Aquantia early 2005 as co-founder. As the company’s chief architect & VP technology, Ramin developed Ethernet PHY products for Cloud and enterprise networks. He holds 80+ granted/pending patents and has published several papers in the field of communication ICs and systems.

technology_ramin_sRAMIN SHIRANI
Sr. VP Engineering

Ramin Shirani has been spearheading products in the Ethernet communications for 25 years and adept in mixed-signal IC design. He is the co-founder and SVP of engineering at Aquantia Corporation. He helped form the team, raise the funds, and run engineering products from concept to production toward market leadership in 10GBASE-T transceivers. +BioLess –

In 1996 Ramin co-founded Enable semiconductor, a mixed-signal Ethernet PHY company, which was acquired by Lucent Micro-electronics in 1999. At Lucent Ramin was the general manager of all Physical layer IC developments ($130M P&L) including OC line of products (OC48, OC192, OC768), Ethernet physical layer devices (10M, 100M, 1G) with cross-functional teams on research initiatives with Bell Labs.

Ramin started his career in 1987 at National Semiconductor as an analog design engineer, and in 1991 he lead the first integrated 10BASE-T MAC and PHY IC which was designed into major customers including Apple PCs. In 1993, he was the technical manager and lead for National’s entry and subsequent 90% market ownership of 100BASE-TX transceivers. Ramin invented the Ethernet auto-negotiation mechanism, which is built into billions of Ethernet devices that have shipped to date. Ramin has 21 granted and 10 pending patents in the area of IC design and communications.