It’s what we do together that sets us apart

Aquantia connectivity solutions power the most advanced products in the world, for the most challenging markets. Join us and work on compelling technologies that contribute directly to out customers’ success.

Senior Staff DV Model Development Engineer

Location:  Toronto, Ontario

To apply for this position, please email: jobs@aquantia.com 

 Responsibilities:

  • Design, maintain and improve C++-based models of hardware components
  • Enable hardware verification by integrating C++ models into UVM testbenches
  • Influence architectural decisions through model-driven experimentation, reporting and analysis
  • Contribute to engineering documents such as specifications and test plans

Qualifications:

 A good candidate has expertise in many of these areas:

  • Modern C++ programming, build tools (e.g. make), Linux
  • Effective software architecture and design, SCM tools (such as git, Perforce, or SVN), software maintenance & testing
  • System modeling or emulation
  • Digital Signal Processing, particularly in communications
  • Matlab or octave
  • Python and other scripting languages (perl, TCL, shell scripts, etc.)
  • Hardware verification using SystemVerilog-UVM, Constrained random verification & SystemVerilog DPI

Important Qualifications:

  • Strong in engineering design and analysis
  • Effective written and oral communication skills and ability to conduct and participate in reviews
  • Enthusiasm for continuous improvement and ability to contribute to process enhancements

Education and Experience:

  • MS Preferred/BS, Electrical or Electronics or Computer Engineering
  • Experience in Functional Verification (preferred), and/or Digital Design
  • Minimum of 8 years for SMTS