Director of DFT Engineering
Location: San Jose, CA
To apply for this position go to: firstname.lastname@example.org
- Lead and manage a team of DFT engineers responsible for scan, MBIST, LBIST and boundary scan
- Responsible for chip DFT strategy, architecture and planning
- Drive DFT flows and methodology development and enhancements
- Collaborate with design, verification, synthesis, PD teams and other cross functional teams for DFT development and debug activities
- Resource and Schedule planning
- Design DFT logic including inserting MEMBIST, boundary scan, scan, and at speed ATPG (Transition Delay Fault Testing).
- Run RTL simulations and gate simulations with SDF to confirm correct functionality of DFT logic.
- Generate ATPG vectors, bring-up and debug patterns, resolve test pattern and coverage issues, support test engineering and operations through qualification, burn-in, and production
- Support failure analysis and fault isolation of pattern failures
- Experience leading and mentoring multi-site DFT teams
- Must have experience inserting, testing, and using DFT logic functions (JTAG, LBIST, MBIST, scan, boundary scan, ATPG) on multiple chips that have been through tape-out and product ramp.
- Must have experience with logic design, especially involving multiple clock domains.
- Experience with automotive flows and qualification highly desirable
- Experience with Perl or other similar scripting languages.
- Experience with silicon lab bring-up.
- Experience operating a tester to debug patterns is a plus.
- Experience with physical design tools, synthesis tools and static timing analysis tools such as PrimeTime is a plus.
- Clear written and verbal communication skills
Education and Experience:
- MS preferred or BS in Electrical Engineering (MSEE), Computer Science (MSCS), or Equivalent.
- Minimum 10 years applicable experience