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DFT Engineer (multiple positions)

To apply for this position go to: jobs@aquantia.com

Responsibilities:

  • Design DFT logic including inserting MEMBIST, boundary scan, scan, and at speed ATPG (Transition Delay Fault Testing).
  • Work with digital design and backend teams on DFT architecture/partitioning.
  • Run RTL, gate, and gate with SDF simulations to confirm correct functionality of DFT logic.
  • Generate ATPG vectors, bring-up and debug patterns, resolve test pattern and coverage issues, support test engineering and operations through qualification, burn-in, and production
  • Support failure analysis and fault isolation of pattern failures

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Qualifications:

  • Must have experience inserting, testing, and using DFT logic functions (JTAG, BIST, mBIST, scan, boundary scan, ATPG) on multiple chips that have been through tape-out and product ramp.
  • Must have experience with logic design, especially involving multiple clock domains.
  • Must have some experience with Perl or other similar scripting languages.
  • Experience with silicon lab bring-up.
  • Experience operating a tester to debug patterns is a plus.
  • Experience with physical design tools (such as PrimeTime) is a plus.
  • Must be able to work within a small team on multiple tasks.
  • Clear written and verbal communication skills

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Education and Experience:

  • BS (MS preferred) in Electrical Engineering, Computer Science, or related field
  • Minimum 5 years applicable experience

Resumes received by Aquantia Corp. from search firms and/or individual recruiters are considered unsolicited and will be kept as Aquantia Corp. intellectual property, or deleted as appropriate, unless a contractual obligation exists otherwise between Aquantia Corp. and a search firm and/or individual recruiter.