DFT Manager
Responsibilities:
• Manage a DFT engineering team while being a hands-on contributor
• Act as the liaison between DFT, test engineering, and operations, to resolve test pattern and coverage issues
• Work with digital design and backend teams on DFT architecture/partitioning
• Design DFT logic (Inserting MEMBIST controllers with repair, boundary scan, scan, at speed ATPG (Transition Delay Fault Testing)
• Run RTL, gate, and gate + SDF simulations to confirm correct functionality of DFT logic
• Generate ATPG vectors, assisting with debug, and other activities to support production
Requirements:
• Must have experience inserting, testing, and using DFT logic functions (JTAG, BIST, mBIST, scan, boundary scan, ATPG) on multiple chips that have been through tape-out and product ramp
• Must have experience with logic design, especially involving multiple clock domains
• Must have some experience with Perl or other similar scripting languages
• Experience with silicon lab bring-up
• Experience operating a tester to debug patterns is a plus
• Experience with physical design tools (such as PrimeTime) is a plus
• Must be able to work within a small team on multiple tasks
Education & Experience:
BS (EE or CS) plus 10 years applicable experience.