DFT Engineer
Responsibilities:
• Designing DFT logic (Inserting MEMBIST controllers with repair, boundary scan, scan, at speed ATPG (Transition Delay Fault Testing)
• Running RTL, gate, and gate + SDF simulations to confirm correct functionality of DFT logic
• Generating ATPG vectors, assisting with debug, and other activities to support operations and test engineering teams
Requirements:
• Must have experience inserting, testing, and using DFT logic functions (JTAG, BIST, mBIST, scan, boundary scan, ATPG) on multiple chips that have been through tape-out and product ramp
• Must have experience with logic design, especially involving multiple clock domains
• Must have some experience with Perl or other similar scripting languages
• Experience with silicon lab bring-up is preferred
• Experience with physical design tools (such as PrimeTime) is a plus
• Must be able to work within a small team on multiple tasks
Education & Experience:
BS (EE or CS) plus minimum 5 years directly applicable experience